A Unique Design Too= l for Improving the Input Match of Low Noise Amplifiers

By Dale D. Henkes=

Figure SEQ Figure \* ARABIC 1, Low Noise Amplifier (LNA)

This article will describe the methods and mechanisms = for trading excess output return loss for improved input return loss while maintaining low noise figure (NF) in a low noise amplifier (LNA) design. Other methods for improving LNA in= put match, such as trading noise match for input match or employing series nega= tive feedback [1], sacrifice gain in the process. While gain reduction may also be t= he result of trading output match for input match, there is at least the opportunity for maintaining the gain approximately constant during the proc= ess since matching gain lost at the output can be picked up by the improvement = in input match.

Figure 1 is constructed to clarify the meaning of many= of the important design parameters. These are impedances or reflection coefficients as seen by looking in either direction across the device (input and output) interface planes. Impedance (Z) and reflection coeff= icient (Γ) are shown for both direct= ions at each plane. Z and Γ a= re related to each other through a given reference impedance (Z_R=) according to the formulas [2][3]:

Equation 1) Γ =3D (Z – Z_R*)/(Z + Z_R) =3D (Z – Z₀)/(Z + Z₀) for Z_R =3D Z₀ (real).

Equation 2) Z =3D Z₀ (1 + Γ)/(1 – Γ).

In keeping with the notation of much of the literature= on the subject, Z_S refers to the transformed source impedance (not the generator impedance). This is the impedance that the transistor sees looking into the input matching network. Z_L is the transformed l= oad impedance that the transistor sees looking into the output matching network (not the load impedance terminating the amplifier’s output port). Z_in and Z_out refer to the input and output impedances of the device/transistor (not the impedances at the input and output ports of the amplifier). Z₁ and Z₂ in Figure 1 represent the generator and load impedances and are usually both Z= 0 (Z₁ =3D Z₂ =3D Z0).

Designing an amplifier for maximum gain (Gmax) at a gi= ven frequency requires the calculation of a unique pair of termination impedanc= es that will provide a simultaneous conjugate match at both ports and yield the maximum gain for the device/transistor used (provided that the device is unconditionally stable at the given frequency). The required terminations can be calculated from the S-parameters of the device [3]. Likewise, a unique pair of termina= tion impedances determine the minimum noise figure and maximum associated gain of the amplifier. However, in th= is case, noise parameters for the device are needed in addition to the device’s S-parameters.

In both of these design scenarios, there is no flexibi= lity in the choice of termination impedances because the solution set is represe= nted by just two points on the Smith chart.&nbs= p; If a compromise can be made in either the gain or noise figure (or b= oth) then the solution set of termination impedances for a given gain and noise figure immediately becomes infinite as represented by circles in the Smith chart instead of just two points. This article will describe how excess output return loss can be trad= ed for improved input return loss while maintaining the noise figure near the optimum value (Fmin) for the amplifier.&nb= sp; The mathematical solution is quite involved and the graphical soluti= on (on a Smith chart) is tedious. Fortunately, the LINC2 program from ACS (Applied Computational Scien= ces, Escondido CA) completely automates this otherwise complicated process, as will be shown toward the end of this article.

The Noise Fig= ure as a Function of Zs

The noise figure of a linear two-port amplifier can be formulated as a function of only four parameters:

1) Fmin, the minimum noise figure of the device/transi= stor

2) Gamma Opt, the optimum source refection coefficient= for achieving Fmin

3) Rn, the device noise resistance

4) Zs, the actual source impedance applied to the inpu= t of the device

The noise figure, F, is then calculated according to t= he following formula [3]:

Equation 3) F =3D Fmin + (rn/gs)|Y_S – Y_O|^2, where Fmin is the minimum noise figure, rn is the normalized noise resistance (rn =3D Rn/Z0),= Y_S is the source admittance (Y_S =3D gs + j bs =3D 1/Z_S),= and Y_O is the optimum source admittance (Y_O =3D go + j bo =3D 1/Zopt).<= /p>

Three of the four parameters in equation 3 are fixed constants that are determined by the device characteristics at a given frequency. It is interesting = to note that, apart from the device constants that cannot be changed by the circuit designer, the noise figure for the amplifier is completely determin= ed by the source impedance Z_S.&nbs= p; Since the noise figure is a function of only one variable, the circu= it designer has only to select a Z_S value that gives the desired no= ise figure. Only one value of ZS (Z_S =3D Zopt) gives the minimum noise figure Fmin. Other values of Z_S yield larger noise figures and the solution set for any noise figure larger than = Fmin is represented by a circle (called a noise circle) on the Smith chart. Many simulation programs, includin= g LINC2, have the ability to plot these noise figure circles as an aid in selecting = the source impedance that will yield the desired noise figure.

Designing for= Minimum Noise and Maximum Associated Gain

A common approach used in the design of RF low noise a= mplifiers is to design an input matching network that will transform the source imped= ance from 50 ohms to the optimum value for minimum noise (determined by Γop= t) and then terminate the output with a conjugate match. This is easy to do since we can ap= ply Γ_S =3D Γopt at the input terminals of the device and calculate the required load reflection coefficient Γ_L =3D Γout* for the conjugate output match.= A circuit simulation can be run on the circuit shown in Figure 2 to determine the output impedance (Zout from Γout) with Γopt as the source termination, or the following formula can be used to calculate this impedance directly.

Equation 4) Γ_L =3D Γout* =3D (S22 + S12 S21 Γ_S/(1 – S11 Γ= ;_S=))* =3D (S22 + S12 S21 Γopt/(1 – S11 Γopt))*

Equation 5) Z_L= =3D Z0 (1 + Γ_L)/(1 – Γ_L)

At this point we have all the necessary information to design the low noise amplifier. Matching networks are designed to transform= Z0 to Zopt and Z_L at the input and output terminals of the device respectively. To complete the circuit, bias netw= orks are designed to feed the supply voltages to the device.

Figure SEQ Figure \* ARABIC 2, Select the Input Impedance and Determine the Output Impedance

Disadvantage = of Designing for Minimum Noise Figure

As can be seen by equation 4, there is only one load impedance, Z_L, that will provide a conjugate output match for a device terminated at the i= nput for minimum noise. With the output terminated with a (conjugate) matched Z<= sub>L= , the input impedance Zin can be calculated according to equations 6 and 7 be= low.

Equation 6) Γin =3D S11 + S12 S21 Γ_L/(1 – S22 Γ= ;_L=)

Equation 7) Zin =3D Z0 (1 + Γin)/(1 – Γin)

However, Zin generally is not equal to Zopt* and so a mismatch occurs at the input port. Therefore, the disadvantage of designing an LNA for minimum noise fi= gure (and maximum associated gain) is that the input will usually be mismatched.=

The amount of mismatch, M, and reflection coefficient,= Γ, can be calculated from equations 8 and 9 respectively [4]:

Equation 8) M =3D (1 - | Γin|^2)(1 - | ΓS= |^2)/|1 = - Γin Γ_S|^2=

Equation 9) Γ =3D Sqr(1 - m)

The mismatch expressed in terms of return loss is:

Equation 10) RL =3D 20 Log(|Γ|)

For minimum noise, Γ_S =3D Γopt and the return loss for this mismatch is:=

Equation 11) RL =3D 10 Log(|1 - (1 - | Γin|^2)(1 - | Γopt|^2)/|1 - Γin Γopt|^2|)

Input Mi= smatch in the Unilateral Low Noise Amplifier

For the simplified unilateral device model shown in Figure 3A, Zin =3D R_{i<=
/sub>
– J X_Ci. The
required input match for gain and best return loss would be Z_S =
=3D
Zin* =3D R_i + J X_Ci.=

As stated previously, the required match for minimum noise is Z_=
S
=3D Zopt. Since there is no c=
ontrol
over Zopt or Zin for the unilateral device, there is no way to achieve the
noise and gain/RL match simultaneously.&nb=
sp;
The resulting mismatch occurs with RL according to equation 11. Without feedback the unilateral de=
vice
will not allow for improving the input match without compromising the noise
figure. Therefore, the method
described next will not work for a unilateral device where S12 =3D 0. However, for most transistors S12
≠ 0 and the following method applies.}

Figure SEQ Figure \* ARABIC 3, Simple Device Model

Trading Outpu= t Match for Improved Input Match

Consider the addition of Cdg (or other feedback mechan= ism) in the bilateral device model of Figure 3B. This feedback allows changes at the device output to be coupled to the input, thus changing the value of Zin. If we can change Zin to make it cl= oser to Zopt* then we have improved the input return loss (while maintaining the minimum noise figure).

The exact dependence of Zin (Γin) on Z_L= (Γ_L) was given in equations 6 and 7. From this relation and the picture of the bilateral device model in Figure 3B, it is clear that some change in Z_L (the load match) will result= in Zin moving closer to Zopt*. T= he main question now is what values of load impedance (Z_L) will res= ult in improved values of Zin.

One value of Γ_L (if it exists) is certain to make Zin =3D Zopt*. It can be found by solving equatio= n 6 for Γ_L in term= s of Γin and the device S-parameters as shown in equation 12:

Equation 12) Γ_L =3D (Γin - S11)= /(S12 S21 – S11 S22 + S22 Γin)

Substituting Γopt* for Γin in equatio= n 12 produces the correct load (Γ_L) for a perfect input RL match and noise match. There are a = couple of problems with this approach. It can produce a very poor output match, often with a RL of only a few dB or e= ven worse. Another potential prob= lem is that the required load may not exist within the Smith Chart boundary and therefore will not be realizable.

What is desired is a method that implements a compromise between perfect output return loss and poor input return loss and vice versa. Referring to Figure 4, the graphic= al solution is a follows:

Figure SEQ Figure \* ARABIC 4, Circle and Impedance Mapping on the Smith Chart

= 1. Plot Γopt on the input plane (Smith Chart representing impedances at the device input= ).

= 2. Map Γopt from the input plane to what would be a conjugate match (Γ_ML) on the output plane using equation 4.

= 3. Plot a mismatch circle (C2 in Figure 4) relative to Γ_ML in the = output plane. Any size circle can be= used initially, but a circle representing a 1.5 VSWR makes a good starting point= .

= 4. Map the output mismatch circle to the corresponding Γin* circle (C3 in Figure 4) u= sing the conjugate of equation 6.

= 5. Find a p= oint on C2 that maps to a point on C3 that is closest to Γ_S= =3D Γopt. Denote the point on C3 as &= #915;in*.

= 6. Construc= t a mismatch circle (C1 in Figure 4) relative to Γin* (fou= nd in step 5) that intercepts the point Γ_S =3D Γopt in t= he input plane.

= 7. Compute = the equivalent input return loss represented by circle C1 according to equation= s 8, 9, and 10. Compute the equiva= lent output return loss represented by circle C2 in the output plane using simil= ar expressions (in terms of Γ_ML and Γ_L).

8. Determin= e if the input and output return loss (step 7) meets requirements. If not, repeat steps 3 through 8 u= sing a different output mismatch circle C2. If the return loss at both ports is acceptable then go on to design = the matching networks to yield Γ_S =3D Γopt at t= he input and Γ_L at the output.

After designing the matching networks and bias feeds, the LNA design is complete. A simulation can be= run on the complete LNA circuit to verify performance. All of the above steps (1 through = 8) are automated in the LINC2 LNA Circles Utility. Selecting Minimum Noise | Fmin, Gain and RL from the view menu performs a= ll these steps in less than one second. A slider control makes the process interactive and intuitive. Moving the slider control from Max Output RL toward Max Input RL makes the tradeoff between output and input return loss automatic. The new match points, all circles, gain, return loss and noise figure are instantly updated when the slider control is moved.&= nbsp;

The LINC2 Circles Utility allows for inputting an exact numerical value for the output return loss instead of using the slider control. Simply press the Enter key, input = the desired output return loss, and click OK.&= nbsp; Once again, the new match points, all circles, gain, return loss and noise figure are instantly updated. When the desired tradoffs have been made, selecting the Match menu automatically designs the matching networks and synthesizes the complete LNA circuit schematic.

Balancing LNA Performance Between Noise Figure, Input Match and Output Match - a Three-Way T= radeoff.

In the last section, a procedure was outlined for trad= ing output RL for improved input RL while maintaining the NF at Fmin (minimum n= oise figure). That procedure is sl= ightly restrictive since the input match impedance (Z_S) is not allowed = to deviate from Zopt. If the two= -way tradeoff of the previous section is expanded to a three-way tradeoff betwee= n NF and RL at both ports, the added flexibility in allowing Z_S to va= ry away from Zopt increases the capability of meeting more demanding RL goals = at both ports.

It is often the case that giving up just a little in n= oise figure can go a long way toward boosting the input return loss without havi= ng to sacrifice too much output return loss.&= nbsp; This is especially true when the noise resistance of the device is small. This is evident by not= ing in equation 3 that the normalized noise resistance (rn) is a direct factor in = how the magnitude of the difference in Γ_S and Γopt adds to Fmin. When rn is small, a sma= ll departure from Fmin results in a relatively large noise circle. For a given NF, this allows Γ= _S (on the given NF circle) to reach closer to the point of best input return loss. In any case, giving up = some NF improves the output to input RL tradeoff regardless of the value of rn.<= /p>

LNA Design Ex= ample

In addition to implementing the two-way tradeoff betwe= en input and output RL, the LINC2 program also automates the three-way tradeoff between NF, input RL and output RL. The procedure is similar to the 8-step procedure outlined above, exc= ept that a noise circle representing a noise figure larger than Fmin will be added. In this case, ΓS will then be located on the noise circle at a point closest to the maximum input RL point, instead of Γopt.

The proposed LNA design example will have the following design goals:

LNA Device: Agilent ATF-54143 FET PHEMT.

DC Operating Point:&n= bsp; Vds=3D2V, Id=3D20mA.

GPS Frequency Band:&n= bsp; 1574.42 to 1576.42 MHz.

Power Gain: > 16 dB.

Noise Figure: < 1.0 dB

Input RL: > 13.98 dB (1.5 VSWR)

Output RL: > 9.54 dB (2.0 VSWR)

The design procedure will be implemented at 1.575 GHz (center of the GPS RX band).

The design starts by selecting Amplifier Design | Low Noise Amplifier from the LINC2 Tools menu. At the prompt the S-par= ameter file name for the ATF-54143 FET device is entered and the LINC2 Circles Uti= lity opens with the device data loaded (Figure 5). The next step is to enter the freq= uency range (1574 – 1576 MHz) and select 1575 MHz from the Frequency menu as the design center frequency.

View | Stability displays stability circles for= the selected frequencies, indicating that the design could benefit from increas= ed stability. The LINC2 LNA desi= gn utility offers several methods for automatically stabilizing a device. When a stabilization method is sel= ected from the Options | Stabilize Device menu, clicking Optimize w= ill generate just enough resistive loading or inductive feedback to stabilize t= he device. For this example, 0.3= 5 nH of common lead inductance was used for improved stability via series feedback. The 0.35 nH inducto= r is placed between the source (common) lead and ground as shown in Figure 5. In this example the inductance val= ue was selected manually (instead of using Optimize) in order to control the amount of feedback short of complete unconditional stability.

Selecting View | Noise, Ga= in and RL from the top menu bar opens the Single Frequency Analysis (Circles) window for automated three-way tradeoff analysis between noise figure, gain= and return loss (Figure 6). The p= rinted data at the bottom of the window in Figure 5 indicates that the minimum noi= se figure at this frequency is 0.36 dB with a maximum associated gain of 16.6 dB. With the output matched (output RL= =3D 50 dB), the input RL is reported as only 6.7 dB.

At this point only two things= need to be done to meet the original LNA design goals. First, we trade off a very slight = amount of noise figure for improved matching conditions. This is done by entering 0.4 dB in= the Noise (dB) input box in the upper right corner of the Input Plane display (Figure 6). Then, the RL slid= er control is moved from Max Output RL toward Max Input RL until the input RL = spec of 14 dB is exceeded. As the = RL slider control is moved, the output mismatch circle grows while the input mismatch circle decreases in size. A check of the output RL indicates that it also exceeds the 9.54 dB = spec by nearly 2 dB.

Figure SEQ Figure \* ARABIC 5, The LINC2 LNA Circles Utility

Figure SEQ Figure \* ARABIC 6, Gain, Noise Figure and Return Loss Tradeoffs Using the Circles Utility

As the Noise, Gain and RL analysis of Figure 6 indicat= es, all specifications have now been met or exceeded as shown in Table 1:

Table 1

Specification	Goal	Design
Frequency	1575 MHz	1575 MHz
Power Gain	> 16 dB	17.12 dB
Noise Figure	< 1.0 dB	0.4 dB
Input RL	>13.98 dB	14.4 dB
Output RL	> 9.54 dB	11.4 dB

The LINC2 program graphically and numerically displays= the source and load impedances required to realize the design goals listed in T= able 1. Z_S is plotted a= s a point at the intersection of the 0.4 dB NF circle and 14.4 dB RL circle. The exact source impedance is prin= ted at the bottom of the window as ZSource =3D 25.45 + J 25.82 ohms. Z_L is plotted as a poin= t on the 11.4 dB output RL circle. The exact load impedance is printed at the bottom of the window as ZLoad =3D 34= .82 + J 22.42 ohms.

The displayed Z_S and Z_L data is required information for designing the input and output matching networks.<= span style=3D'mso-spacerun:yes'> However, LINC2 automatically takes= this data and synthesizes the complete LNA schematic including the matching netw= orks and device stabilization components.

LINC2 LNA Synthesis

The LINC2 LNA design module offers many approaches to = low noise amplifier design and synthesis. The following design methods are automated in the LINC2 LNA design t= ool:

*Minimum noise.

*Maximum gain.

*Noise and gain tradeoffs (match varies between Fmin a= nd Gmax points).

*Minimum noise with improved input RL (trading off out= put RL).

*Low noise with improved input RL (trading off NF and = output RL).

*Available power gain design.

*Operating power gain or transducer power gain design.=

As is the case for each of these design methods, the three-way design tradeoff presented above is completed by simply selecting = the desired matching network topology from the Match menu. An LNA schematic is immediately synthesized that captures the design’s performance. When a lumped L network with a ser= ies C and parallel L topology is selected from the Match menu, the LNA schematic = in Figure 7 is generated.

Clicking Analyze in the schematic window runs a circuit simulation producing the results shown in Figures 8 and 9. The simulation results for the des= ign frequency of 1575 MHz were exactly as predicted with gain =3D 17.12 dB, inp= ut RL =3D 14.4 dB and output RL =3D 11.4 dB.

Figure SEQ Figure \* ARABIC 7, LINC2 Synthesized LNA schematic

Figure SEQ Figure \* ARABIC 8, Gain (S21) and Return Loss Simulation Results

Figure SEQ Figure \* ARABIC 9, Input and Output Return Loss Simulation Results

The next step is to add the bias networks and construc= t the 0.35 nH source lead inductor from microstrip transmission lines and ground = vias as shown in Figure 10. The component values in Figure 10 have been changed to the nearest available standard value. The shunt inp= ut inductor is connected to the gate supply and a 68 nH choke is used to suppl= y DC to the drain.

Design Verification

Running a simulation of the LNA circuit in Figure 7 pr= ovides a certain level of design verification since the computer methods and algorithms used in the LINC2 circuit simulation are very different and independent from the synthesis algorithms used to generate the design in Fi= gure 6. Ultimately, however, the d= esign must be verified by building a prototype and testing it. The circuit in Figure 10 was built= and tested. The measured performa= nce was remarkably close to the results obtained from the LINC2 circuit simulat= ion (Table 1 and Figures 8 and 9).

The measured versus simulated results are shown in Tab= le 2. Figure 11 plots the simula= ted and measured gain and noise figure. Figure 12 plots the simulated and measured input and output return loss. The measured gain, NF a= nd input RL agreed with simulation within a fraction of a dB. The output return loss measured lo= wer than the simulated value by about 1.25 dB.

Summary

This LNA design example demonstrated how the unique fe= atures of the LINC2 LNA design tool can simplify the complex task of balancing a number of competing design tradeoffs. LINC2’s automated interactive optimization at the design level (during the circuit synthesis procedure) can be far more effective than cir= cuit level optimization. In additi= on to being faster than circuit level optimization, interactive optimization at t= he design synthesis level allows for optimization of the circuit topology, not just the component values of a given topology. For example, circuit level optimiz= ation starts with a given circuit topology while in the LINC2 LNA synthesis tool = the circuit topology (matching networks) are selected last, after all tradeoffs have been made and the design has been optimized.

It is not uncommon for leading RF/microwave EDA softwa= re packages to have utilities for plotting various circles on a Smith Chart to= aid in the design of low noise amplifiers.&nbs= p; However, these other circle plotting tools are usually manual in nat= ure in the sense that they require the user to know what circles to plot and ho= w to relate the circles to one another and to the design flow. The LINC2 Circles Utility is compl= etely automated and linked to the design flow.&n= bsp; This allows the user to focus on the design goals and the parameters that affect performance rather than on the construction of circles.

The underlying math routines and LINC2 proprietary algorithms keep the circles and printed design and performance data updated= as the user enters specifications or makes design tradeoffs. This highly automated LINC2 design= tool makes the various constant circles practically obsolete because the user is guided through the design procedure without having to construct the circles= or even having to know what they mean. However, experienced designers who are accustomed to designing LNAs = by manipulation of the constant circles will appreciate the visual feedback provided by the automatically displayed circles and the fact that they can = also be manually constructed by the user if desired. This kind of graphical feedback ca= n help the user know what is possible in regard to performance and why. This level of insight into the parameters that affect the design and its performance as well as the insight into the design methods and synthesis process cannot be provided by simply using a circuit level optimizer.

LINC2 is a high performance, low cost, RF and microwave design environment providing automated design, circuit synthesis, schematic capture, simulation, optimization and yield analysis in one integrated pack= age. LINC2 is available from ACS (Appli= ed Computational Sciences), Escon= dido, CA. More information on LINC2 can be f= ound on the web at www.appliedmicro= wave.com.

Figure SEQ Figure \* ARABIC 10, Prototype LNA Circuit Schematic

Table 2, LNA Simulated Versus Measured Results

Specification	Goal<= /span>	Simulation	Measured
Frequency (MHz)<= o:p>	1574 - 1576=	1574	1575	1576	1574	1575	1576
Power Gain (dB)<= o:p>	> 16	17.13	17.12	17.11	17.75	17.74	17.71
Noise Figure (dB= )	< 1.0	0.4	0.4	0.4	0.68/0.38*	0.67/0.37*	0.66/0.36*
Input RL (dB)	> 13.98<= /o:p>	14.48	14.47	14.46	14.03	14.02	14.02
Output RL (dB)	> 9.54	11.39	11.4	11.42	10.18	10.17	10.17

*NF after a= djusting for 0.3 dB total front-end component losses in cable, connector and input microstrip.

Figure SEQ Figure \* ARABIC 11, LNA Simulated and Measured Gain and Noise Figure

Figure SEQ Figure \* ARABIC 12, LNA Simulated and Measured Return Loss

References

[1] Dale D. Henkes, “LNA Design Uses Series Feed= back to Achieve Simultaneous Low Input VSWR and Low Noise”, Applied Microw= ave & Wireless, October 1998, pp. 26-32.

[2] Janusz A. Dobrowolski & Wojciech Ostrowski, “Computer-Aided Analysis, Modeling, and Design of Microwave Networks”, Artech House, 1996.

[3] Guillermo Gonzalez, “Microwave Transistor Amplifiers - Analysis and Design”, Prentice-Hall, 1984.

[4] Robert E. Collin, “Foundations for Microwave Engineering” 2^nd edition, McGraw-Hill, 1992.

[RETURN]<= /p>